1. Field of the Invention
This invention relates to metal layer patterns of a semiconductor device and a method for forming the same, and more particularly to metal layer patterns of a semiconductor and a method for forming a photomask to pattern metal layers of a semiconductor device which prevents the characteristics of the device from being deteriorated during the etching process of the metal layer.
2. Description of the Prior Art
Generally, the dry etching process using plasma is performed by the strong reactive characteristics of ions in the plasma, which are accelerated by the electrical field formed between the electrodes of the chamber, with the etched layer. The layer is etched by the reaction of the accelerated ions and the atoms of the layer.
The dry etching process using plasma is useful for manufacturing high density semiconductor devices, for example 1 Giga DRAM. Therefore, the dry etching process using plasma is becoming more important in the manufacturing of high density semiconductor devices. Also, the dry etching process is frequently used to etch the metal layers of the semiconductor devices.
In the conventional dry etching process of the metal layer, the metal layer itself is used as an electrode to flow electrical current induced by the plasma.
Referring to the drawings, FIG. 1A is a schematic cross sectional view of a conventional semiconductor device. As shown in the FIG. 1, the conventional semiconductor device Includes a semiconductor substrate 1, a gate oxide layer 2, a field oxide layer 3, a gate electrode 4, an impurity area 5, an interlayer insulating layer 6 and a metal layer 7. Note that the impurity area 5 is not a source/drain area of the transistor of the gate electrode 4, and forms an electrical contact with the metal layer 7.
The electrical contact of the metal layer 7 with the impurity area 5 is used to flow the above mentioned electrical current, which is induced by the plasma in the dry etching process for patterning the metal layer 7, to the silicon substrate 1.
FIG. 1B is a layout diagram of the photomask for forming the conventional metal layer 11 of the semiconductor device. As shown in the FIG. 1B, the metal layer 11 has different spacings between patterns depending on the location of the patterns.
However, the above mentioned conventional metal layer 11 of semiconductor devices has the problem of loading effect clue to the different spacings. The loading effect results in a different etch rate, depending on the locations of the etched patterns. Therefore, in case the etching process is controlled with the lowest etch rate, over-etched patterns are produced and the gate oxide under the over-etched patterns are deteriorated. Furthermore, the over-etching will cause a greater current to be induced by the plasma and the needed contact area to flow the current to the substrate 1 will be greater.